In this project I designed and layed out a StrongARM comparator latch, used in the strongARM processor by Digital Equipment Corporation's StrongARM microprocessor. The basic latch design was proposed by Toshiba Corporation's Kobayashi et al. in their paper titled "A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture" from 1992 for a robust sense amplifier in an effort to save power dissipation in memory chips. It is a great candidate to be utilized in ADCs.

Key features of the StrongARM latch are the following: 

1) Rail to Rail output 

2) Zero static power consumption

3) Low input offset voltage

The StrongARM latch goes through three different phases: precharge, amplification, and regeneration.

Zero static power consumption can be seen after the regeneration phase when the cross coupled pair above the differential input devices turn off after the regeneration phase, cutting off the path from supply to ground. Power is only consumed when switching and can be quantified using the relation fclk(2*C*Vdd) where C is the capacitances seen at the drain of the input devices and output nodes of the latch.

The circuit is designed using SkyWater 130nm technology. Layout extraction and simulations were conducted using Cadence Virtuoso.

The entire schematic was designed using the following topology shown in the figure below and included output inverter buffers. Top PMOS devices are used during precharge when clock is off to charge all nodes up to supply. We are given a maximum width budget of 5um for all clocked transistors, which means we need to budget wisely. Each PMOS device is used at minimum width (0.42u) since it is only used in the precharge state, speed isn't a large factor for these devices. This leaves us with the tail current. Tail current was increased to 2um for more bias current to maximize speed. For all other devices, Input devices widths were increased to 3um to allow greater amplification, speeding up the amplification phase.

Both a narrow and wide(0.5V & 1.5V) voltage difference are simulated just for comparison. For a smaller voltage difference a rise time of 153ps is observed, while a wider voltage difference provides 71.3ps of rise time. The power consumption for the circuit at 10mV difference is evaluated to be 32.2uW of power consumption, contributed from switching.

Next is the design of the layout of the comparator. Since this is a differential topology, it is best to place tail current in the middle and layout the devices in a similar fashion to the topology. A compact design is preferred for the layout, minimum size that was achieved during layout was 5.61 by 9.01 microns (50.54um^2). The difficulty with layout was the cross coupling scheme, with each differential side mirrored, the gates at the outer NMOS devices had to be connected to the other side. With a little bit of time and elbow grease it could be done however.

After layout had passed all DRC and LVS rules, extraction of the layout was completed using Calibre's PEX tool modeling resistances, capacitances, and cross coupled capacitances. The extracted layout was then placed into the same testbench and simulated to evaluate and compare results.

From simulation rise time was observed to be roughly 287ps for a 10mV difference. That is almost double the rise time of the pre-layout. We also observe a similar trend with the average power which goes up to 58.4uW after layout.

References:

B. Razavi, “The design of a comparator [the analog mind],” IEEE Solid-State Circuits Mag., vol. 12, no. 4, pp. 8–14, Nov. 2020.

B. Razavi, "The StrongARM Latch [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, vol. 7, pp. 12-17, 2015 

J. Montanaro, R. Witek, K. Anne, and A. Black, “A 160-MHz 32-b 0.5-W CMOS RISC microprocessor,” IEEE J. SolidState Circuits, vol. 31, pp. 1703–1714, Nov. 1996. 

T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture,” in Proc. VLSI Circuits Symp. Dig. Technical Papers, June 1992, pp. 28–29.