Tape out process of an 8.5GHz Charge Pump Phase Locked Loop. Design consists of: Phase-Frequency Detector, Charge-Pump, Type I LC-VCO, and CMOS based Frequency Divider.

An 8-bit static register containing eight resettable flip flops driven on a 500MHz clock and containing a primary latch and secondary latch.

StrongArm Comparator Latch for use in ADC's. A modified topology consisting of four pre-charge switches.

Frequency divider schematic and layout which divides an input clock frequency by half.