A design of an 8-bit resettable static CMOS register is shown below with schematic, layout and extraction process. The 8-bit register is comprised of static latches that are driven by a 500MHz clock. Design is processed using SkyWater 130nm technology.

Pre-Layout

Register Design

Each flip flop processes one bit, therefore an 8-bit register would be composed of eight flip-flops in parallel. A testbench was designed to be used to simulate and evaluate proper functionality before moving onto layout. Random streams of data were provided as input for the register. A pulse of 500MHz is fed into the circuit as a clock. Reset is also simulated using a pulse that can turn on within the circuit. Average power consumption pre-layout was calculated to be ~15.9uW, as shown in the simulation figures. Calculations were made without reset functionality as to get the most accurate results of power consumption over the full period of the simulation.

We can also see from the simulation that reset functionality works properly, setting all outputs to low regardless of input.

Layout

For the register layout, each flip-flop cell was stacked in a 4x2 fashion and routed to all the clock, reset, supply, and ground signals together. Each of the four cells on the right is mirrored for easier global routing. Compact rectangular design allows for easy placement in higher abstraction levels. Using Calibre DRC and LVS error check was conducted to give the OK on continuing with parasitic extraction for accurate simulation.

Post-Layout & Extraction

After layout of the entire register was complete, using PEX extraction tool, the parasitic properties of the circuit were extracted from layout. Complete extraction was conducted to gain parasitic resistance, parasitic capacitance, and coupling capacitances. Extracted circuit was placed in the testbench and simulated. As it turns out, post extraction increased power consumption up to 20.9uW, which is less than double the pre-extraction power consumption.