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In this project we present the design, layout, and extraction of a ring oscillator. This was the first design conducted in a series of CMOS IC design projects as the simplicity of the circuit itself makes it a good candidate for beginning IC designers to get familiar with the design flow.
Introduction
Introduction
The ring oscillator consists of an odd number of inverting stages in a feedback, while even number of inverters create a latch. The resulting frequency of the ring oscillator is 1/(2*N*Td) where Td denotes the propegation delay (RC) of the inverter and N is the number of stages. The power consumption follows the rule of dynamic power consumption where P = N*fosc*Cu*Vdd^2.
In our design we will be using a 3 stage ring oscillator and measure its frequency and power consumption. We are given the following sizing and parametrics:
Wp & Wn = 2um
L = 150nm
Vdd = 1.8V
The design will also include a source follower following the ring oscillator to provide it some driving load.
Pre-Layout
Pre-Layout
Ring Oscillator Design
Ring Oscillator Design
The following figure presents the ring oscillator cell with a source follower as a driving load. Each FET is of the size of 2um with the source follower containing a termination resistance of 50Ohms at the output and driving capacitance of 1pF to simulate the ring oscillator driving test equipment.
Simulation
Simulation
We evaluate the schematic design by placing the cell in a testbench and analyze every intermediate node in the circuit (V1,V2,V3). No input stimulus is necessary as the ring oscillator will kick start via truncation and supply noise. We verify that the oscillation frequency is 4.9GHz with an average power consumption of 1.2mW
Ring Oscillator Waveforms
Layout & Extraction
Layout & Extraction
Layout
Layout
The layout of the ring oscillator was performed with shared diffusion in an effort to minimize extra diffusion parasitics. The source follower also contains multiple via taps to minimize resistive parasitics at the gain which will limit the frequency of the oscillator.
Post-Extraction Simulation
Post-Extraction Simulation
We evaluate the extracted design analyze every intermediate node in the circuit (V1,V2,V3) to ensure proper functionality. We observe that the oscillation frequency is 3.46GHz with an average power consumption of 1.382mW. This is a 29% drop in frequency and 15.5% increase in power consumption compared to the pre-extracted schematic. A larger drop in frequency is observed compared to a marginal increase in power.
Ring Oscillator Waveforms
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