8.5GHz Charge Pump Phase-Locked Loop

These past months me and my partner have designed, laid out, verified, and taped out an 8.5GHz Charge Pump Phase-Locked Loop(PLL) using 130nm Skywater PDK. The initial proposal was to design for 10GHz operation since it was in the list of suggestions provided by our advisor, Dr. Behzad Razavi. Unfortunately due to the limitations in technology, we found out during the final process of post-extraction verification that it was not possible to achieve such high of a speed, meeting all process corners, within our power budget(20mW, 30mW after pad integration). This enabled us to lower the speed down to 8.5GHz output, this turned out to be the fastest possible speed, nonetheless we are grateful that we had even tried pursuing such high speeds within our technology. This led to discoveries in optimizing our circuit during layout, i.e. trying to minimize parasitic loss in the divider through via and wiring optimization. Our efforts led us to a very high speed, low power PLL. This effort was conducted from February to end of May 2023, and physical testing of the chip will begin as soon as we recieve our taped out chip by the end of September 2023.

CORE PLL DESIGN

Fig. 1 Complete PLL Schematic Blocks

The Charge Pump PLL topology consists of four main components: Phase Frequency Detector(PFD), Charge Pump, Voltage Controlled Oscillator(VCO), Frequency Divider. Initial Design for 10GHz operation at circuit level.

Phase Frequency Detector (PFD)

The Phase Frequency Detector is implemented using two resettable D-Flip Flops, using a cross-coupled NOR gate implementation, that are both reset using an AND gate when both outputs are high. The two signals being compared in the PLL (reference and divider output) are fed into the clock input of the flip flop with data connected to VDD. The leading signal latches the corresponding Flip Flop output to VDD, which is then reset when the phase lagged signal arrives due to the AND gate connection. Thus this type of circuit provides information about phase differences between two clocks and which signal is leading or lagging.

Fig 2. Example of an PFD Topology [Razavi]

Fig 3. NOR gate implementation

Fig 4. PFD schematic

Sizing for NOR gates was based on Pelgrom's law, where addresses the inverse relation between threshold mismatch and gate sizing. In other words, smaller transistor sizes are more susceptible to greater variations in process[Ali Sheikhoslami]. This leads us to avoid minimum sizing transistors(42um). Trading off speed and power for a guarantee that our chips can work out of the fab. However with the PFD operating at such a low frequency, this is much of a trade off. Later on these mismatches become of greater importance when dealing with current mirror mismatch.

Fig 5. Layout of PFD

Fig 6. Charge Pump Topology

Fig 7. Loop Filter Topology

Charge Pump/Loop Filter

The role of the charge pump and loop filter is to translate the phase differences from the PFD output into a DC voltage for the VCO to read. The Charge Pump essentially a charge injector while the loop filter is an integrator that averages out the up/down output signals from charge injection.

The charge pump design is based off of the gate switch topology where feed forward capacitors are connected to the switches in providing faster switching to better the current alignment.

Current mismatch is an issue in the charge pump topology that presents itself. This can be caused by mismatch due to channel length modulation or random mismatch due to PVT. The mismatches can be mitigated by increasing transistor widths, but at the expense of speed. One way to get around this is by increasing the length of the charge injecting transistors, whilst also adjusting the width accordingly in an effort to better linearity. Reduction of current mismatch by increasing length from 150um to 1um, allows for a large output range,0.33-1.59V, with about 100uA from both the up and down current branches at less than 20% current mismatch. Double the improvement from before which was at a range of 0.66-1.26V

Fig 8. Charge Pump Schematic

Fig 9. Current mismatch Plot Pre Extraction at TT

Fig 10. Current mismatch Post Extraction

Fig. 11 Charge Pump UP/DOWN output current

Figure 8 and 9 shows a comparison of mismatch pre extraction and post extraction. Increasing the compliance range by +/- 50% can allow for better range post extraction.

RED curve is PMOS current, BLUE curve is NMOS current, TEAL is mismatch

Figure 10 shows the Up/Down output currents Pre and Post Extraction comparison at TT.

RED/ORANGE curves are UP current Pre/Post Extraction

BLUE/TEAL curves are DOWN current Pre/Post Extraction

Fig. 12 Loop Filter Layout

Fig. 13 Charge Pump Layout

Fig. 14 Cross Coupled VCO topology[Razavi]

Voltage Controlled Oscillator

The Voltage Controlled Oscillator(VCO) primarily serves the purpose of converting the DC voltage coming from the loop filter into an output frequency.

The VCO of the PLL requires a robust oscillator topology that can achieve all the specified targets shown above without sacrificing too much of the other components. Ring Oscillators introduce too much phase noise while having a lower operating range at 130nm. This does not prove as a viable option, therefore an LC-VCO is the best choice to achieve a 10GHz output with lower phase noise at the cost of area and power consumption.

The LC-VCO has various topologies to choose from such as Colpitts, Hartley, Clapp, etc. Cross-coupled schemes prove to be the best choice since it would not require a lot of gain to retain stability, thus being the most robust option for our needs.

We start out by determining the output swing of the VCO. An output swing of 1.5V peak to peak is quite high, which induces stress onto the MOSFET, however this allows for high rail to rail swing to allow for the frequency divider to switch across corners. This was discovered during iterations to allow for full operation at slower corners.

The inductor designs were provided to us by Dr. Razavi. From a list of inductor designs we had determined to use a 1.5nH inductor which had a higher quality factor(Q) at speeds above 7GHz(this information was provided to us in a document compiled by the inductor designer). From this we can determine the capacitance needed to achieve the target speed(100fF after layout iterations).

The varactors are designed using NMOS devices from the Skywater PDK where drain and source are tied together to imitate capacitive effects. We want to retain minimum lengths for the varactors, and increasing width adds more gate resistance to the output node which pulls the tail current down to triode region. For these reasons we can increase KVCO by adding more fingers to the varactors. In this case only node capacitance will increase at a faster rate, but this can be controlled easily by lowering output capacitor. This results in the varactors having 1.5umx11 fingers each.

It is very vital for the VCO to have symmetric characteristics. For this reason two capacitors are introduced at the output node, amounting to 96fF effective capacitance, as well as a dummy transistor on the tail current transistor with gate source tied.

Transistor sizing:

Tail current: 7um x 5 fingers + 1 dummy finger

Cross-coupled Devices: 3um x 6 fingers each

Varactors: 1.5umx11 fingers each

Self-biased inverters were introduced at the output to bring the output common mode from 1.8V to 0.9V. The self biased inverter can act like an interface between the VCO and dividers as well, to be able to drive the VCO output to the dividers without signal loss when operating at very high speeds.

Fig. 15 VCO schematic

Fig. 16 VCO layout without inductor

Fig. 17 Self Biased Inverter Layout

Frequency Divider

The Frequency Divider is the most sensitive, as well as the most difficult to design, component of the entire PLL. The divider interfaces with the highest operating speed in the PLL, being the output. The design, layout, and placement need to be considered cautiously as parasitics can dominate very easily. This becomes a challenge for us as we are operating at 8.5GHz at 130nm!

Of course using CML latches can allow for some some leverage, but at the cost of excessive power consumption. We were only given a 20mW power budget and the CML latches we have tested operate at 16mW at FF corner. On top of that, the lower speeds will be utilizing frequency dividers suitable for lower speeds, which means we would need a CML to CMOS logic converter. This leaves us with strictly CMOS devices, which cut the power of the entire divider down to lower than 8mW of total consumption. Area will also smaller as a result as well.

The entire divider comprises of the following:

Front End Driver
High Speed (8.5 - 2GHz) - Extended True Single Phase Clock (E-TSPC) + CMOS buffer to drive front end and second divider
Middle Speed(2-250MHz) - True Single Phase Clock (TSPC)
Low Speed(250-65MHz) - Static Latches

Fig. 18 Entire Divider Chain Blocks

E-TSPC Divider

The front-end divider is sized specially for 8.5GHz input. At these high frequencies, to avoid the use of current mode dividers, dynamic logic is a suitable candidate for the front end. The E-TSPC can achieve faster speeds than the regular TSPC[Navarro]. However the difficulty is finding the right sizing to prevent fighting between the NMOS and PMOS of each stage to the point where the logic is ambiguous. This is one of the issues that were observed with the design of the E-TSPC divider.

The E-TSPC divider also has difficulty driving loads of comparable sizing. The proper E-TSPC divider needs a good amount of current to operate at a high speed, thus a wider transister. However this makes it difficult to be driven. Two buffers, one prior to each E-TSPC divider, are added to allow the signal to be driven properly to the E-TSPC.

Fig. 19 Front End E-TSPC Topology

Fig. 20 Second Buffer Topology

Fig. 21 Second E-TSPC Topology

Fig. 22 Third E-TSPC Topology

Fig. 23 TSPC Topology

TSPC Divider

The TSPC divider has similar principles to the E-TSPC that was previously mentioned. After all the E-TSPC is a derivative of the TSPC logic family. The TSPC is a good candidate for high speed due it's reliance on only a single clock. The TSPC divider uses minimum sizing which is already sufficient enough for it's operating speed. This allows for lower power and size consumption.

Static Latch

Dynamic logic comes with current leakage issues. This becomes more apparent at lower speeds, when the branch's off state occurs for longer time periods. To mitigate this issue, static latches are used for the last two frequency dividers that operate at frequencies lower than 250MHz. The static latches utilize complementary clocks that feed through the transmission gate. A transmission gate is placed between the master and slave latch to cut off unnecessary power consumption. Later on we will discuss the issue of minimum sizing and process variation, however these are rather important for matching devices, and switches at lower speeds such as static latches probably won't be affected as much.

Fig. 24 Static Latch Topology

Fig. 25 Divider Layout

Current Mirrors

In our circuit, the VCO and charge pump are the only two blocks which require a current mirror source. Current mirrors need to be robust against PVT variations. This is especially true when they need to supply large amount of current to the mirrored device. Unfortunately at smaller sizing's the process variations, which in turn causes current mismatch in branches, are more apparent. This is is explained in Pelgrom's law[Ali Sheilkholm] where gate size and the threshold voltage variation are inversely proportional. For this reason we try to avoid minimum sizing of transistors for our mirror devices(0.42um). On top of that we also want symmetry for our mirrored devices. In this case we add an extra dummy finger to our current mirror devices to have equal symmetry on both sides. Resistors on all the layouts will also be split into multiple resistors in series to have more compact spacing. Downside to all of these is the increased size of the transistors taking up space, however the design does not increase the mirrored devices sizing by a significant amount.

Fig. 26 Current Mirror Layout

PLL CORE LAYOUT

The entire layout for the core of the circuit is shown below. We made an effort to keep the design as compact as possible. This means bring all blocks as close together as possible without having any DRC errors. For differential devices, such as the VCO, we are interested in sustaining symmetry between devices. The distances between the VCO and self-biased inverter are equidistant. We also tried to make an effort to minimize as many 90 degree corners as possible for the design to reduce parasitic inductance in the wire.

Fig. 27 PLL Core Circuit Layout

PAD INTEGRATION

Fig. 28 Pad Frame Pin Placement

PIN LAYOUT

The pin placement within the pad is shown to the left. We have the supply pins surrounded by ground pins and all ground pins are connected to each other via the pad ring. We designate three supplies for top, right, and bottom portion of the circuit. However because the frequency divider is the most sensitive part of the circuit, it will be using it's own designated supply pin so that no switching noise will affect it's performance. As a result it will have it's own designated decoupling capacitors. The right VDD will be supplies for the output devices (self-biased inverter, VCO, Output Buffer), and the bottom VDD(VDD_LEFT1) will be used for all other components in the PLL. Some supplies are split between two pads to lower the effective inductance from the bond wires.

Divider Output Pad Buffers

When testing the PLL in lab, we would also like to analyze the output of the frequency divider to comparison with the incoming reference frequency. For this reason a buffer is added to give enough driving strength of the divider output to the pad. The output to the pad is inverted due to the small inverter just before the buffer.

Fig. 29 Divider Inverter

Fig. 30 Divider Output Pad Buffers

Fig. 31 Divider output Pad Buffer Layout

Fig. 32 Output Buffer Layout

VCO Output Buffer And PLL Output Interface

To drive the high speed signal from the small self-biased inverter to a pad of 600fF, we need an output buffer large enough to drive the pad. Since we are using a spectrum analyzer to measure PLL output, we do not need large output swings at the PLL Output, likely around 100mV should suffice(as long as it's well above the noise floor).

The challenge here was that at 8.5GHz, driving the signal with proper buffer sizing's(x4, x16) was difficult with the Skywater 130nm technology. Odd sizes such as x1.25 of x1.4 worked better for this technology, but that meant more unnecessary fingers in the chain. This was an issue we faced with the dividers, which is why the output target frequency was dropped from 10GHz to 8.5GHz.

Rather than increasing width, the approach was the increase fingers. Because this was a major factor also reducing gate resistance, while beefing up the device capacitance for driving force. After some iterations, it was found that 20 fingers x 4um for the output buffer was sufficient enough to drive the signal to a 50Ω terminated device, and 600fF of capacitance from the pad frame, providing 100mV output.

Decoupling Capacitors

Decoupling capacitors were added to the pad to lessen the effect of supply noise on the chip. Adding decoupling capacitors across any open spaces in the chip. The ports where the decoupling capacitors are connected to are the three supply pins(denoted with VDD_LEFT, VDD_LEFT1, VDD_RIGHT).

The total effective decoupling capacitance in the entire chip is the following for each pad:

VDD_LEFT: 230pF

VDD_LEFT1: 6.5pF

VDD_RIGHT: 131pF

Fig. 33 Decoupling Capacitors

Fig. 34 Entire PLL circuit with pad frame

SIMULATIONS

Fig. 35 Simulation Test Bench

We use inductors in the test-bench to provide bond-wire inductance modeling. 2nH of inductance is used to provide us with the worst case and ensure our chip can properly operate in such an environment. Normally this is a pessimistic approach as 1-2nH suffice.

600fF of pad capacitance is included in the test bench, since this test bench does not include the pad frame(simulation with R extraction of the pad frame takes a very long time). This will allow us to include the effect of pad capacitance on the signals coming in and leaving the pad.

On top of that a 50Ω termination resistance is included in the ports of measurement(divider output and PLL VCO output) as the measuring devices used in lab utilize such termination. Incorporating termination and pad capacitance modeling will provide a close to real-life prediction of measurements and ensure that the measurements in the lab will be legible.

We use on-chip ground to do internal measurement analysis since a lot of noise induced by the inductor will be apparent with off chip analysis.

It is observed from simulations that the PLL Consumes 27.25mW when measuring the entire chip with decoupling capacitors, using a 1.8V power supply. This is below our 30mW budget for the entire chip.

Fig. 36 Locking Characteristics at TT

Fig. 37 PLL Output Inside Chip

Fig. 38 PLL I/O Output

Fig. 39 PLL Divider I/O Output

Fig. 40 Reference Signal vs. Divider Output

Fig. 41 VCO Output

Fig. 42 PLL Locking at TT (Off Chip GND Analysis)

Fig. 43 VCO Output

Fig. 44 PLL Locking at TT (Off Chip GND Analysis)

PCB DESIGN

The next step in the process is the PCB design and layout. It is imperative that we retain characteristics on the PCB that allow for high speed signal transfer. Our design approach is outlined below.

Fig. 45 PCB Schematic

Schematic

We first outline our bill of materials(BOM). The key components of our BOM is the potentiometer, decoupling, capacitors, and SMA connectors. We look for decoupling capacitors that would have a really high self resonant frequency(SRF), this is important since our capacitors need an SRF as close to RF for maximizing rejection of such signals in the DC pins. Our decoupling capacitors use an SRF of about 1.2GHz. This was the largest SRF found at a reasonable size and capacitance(100pF with 0812 capacitors). We use 0812 sizing so that the capacitors may also be soldered by hand. As a general rule of thumb, the board decoupling capacitances are 10 times larger than the chip decoupling capacitances(~2nF).

We implemented potentiometers as an external control for adjusting the current mirrors in the event of PVT mismatches. To reject supply noise in affecting the control voltage a shunt capacitor from the potentiometer to ground is placed. A static series 2kOhm resistance is also added in conjunction with the potentiometer to prevent direct connection to supply onto the pin. Once the proper resistance of the potentiometer is found that counteracts the PVT variation of the current mirror resistance, a resistor footprint is placed onto the board so that we can solder a resistor of that value onto the board permanently.

A 50Ohm SMA connectors are also an appropriate choice for such high speed signaling. A 50Ohm termination resistance is place between the SMA connector and output pins for all high speed ports (Output, Input, and Divider Output Pin).

Banana plugs are used for testing purposes, but a standard 4 pin power jack is also included for all power and ground pins post testing.

Layout and Routing

The MOST important section of our board is the high speed traces. We decide to go with a coplanar waveguides for our traces. We do this by surrounding our traces with ground plane. Ideally less routing density would be preferably to avoid the possibility of crosstalk between traces and interference, therefore we go with a 4 layer board design with high speed traces(RF_out, Input, Divider Output) at the top. We also place the output pin of the chip as close to the SMA connector as possible at around 10mm tracing. Avoiding 90 degree traces to minimize inductance caused by bends as well.

Thickness of board, trace widths, dielectric, etc. are calculated to allow for 50Ohm trace impedance.

Fig. 46 High Speed Trace Routing

The decoupling capacitors are laid out with the smallest capacitor value closer to the chip pins, and the larger capacitors further out from the chip pins.

Stitching vias are also added to equalize the distribution of electric field between the ground plates at every layer.

Off board components will include a bias-T network for the input 65MHz signal.

The entire PCB is about 2.5 x 2.5 inches, essentially utilizing very compact sizing.

Fig. 47 PCB Layer 1

Fig. 48 PCB Layer 2

Fig. 49 PCB Layer 3

Fig. 50 PCB Layer 4

Fig. 51 PCB 3D view

Bill of Materials

UCLA 8.5GHz PLL.xlsx

TESTING & VERIFICATION

Once we obtained our chips back we bonded the chips to our board's ground paddle and soldered the necessary components. We initially conducted a continuity test to make sure that there were no shorts onto the board before and after bonding the chips. Due to an error with the bonding, almost everyone's chips were shorted to ground due to the terminals of the bond wire touching the ground paddle. In order to prevent this we would have to use a ball bonding technique which prevents the bond wire terminals from touching the ground ring. This became a more accurate and reliable solution.

One issue that we have noticed was that the supply for the divider and VCO were shorted together. Luckily this doesn't affect the functionality of the chip by a large margin. Now that the continuity test is good, we proceed with the testing phase.

Fig. Close up of ball bonding on the PLL

Fig. The four boards that will be tested

We decided to verify our PLL for the following metrics at nominal and +10% supply:

Output center frequency

Lock range

Reference spurs

Phase Noise

Power consumption

We were given 4 boards for testing, denoted by serial numbers(SN1-SN4). Two of each boards uses epoxy coating on the chip. We will be testing each of these boards and note down each of their performance and differences.

We found out that SN1 became defective after our second test. The loss of functionality is likely due to ESD. Therefore we will proceed the test with SN2-SN4.

Measurement Proceedure

Phase noise is determined by finding the power at the 1MHz frequency offset. Unfortunately the output signal is so low that it is difficult to determine the actual phase noise via the spectrum analyzer. Therefore we use the following relation to determine phase noise:

Phase Noise = (ΔdB + 10log(RBWin Hz)

Where RBW is the refresh bandwidth.

To measure lock range we sweep the reference up until the output begins to show large phase skirts, which is an indication of the PLL not locking. We then note the output lock range and the reference frequency which corresponds to that.

Reference spurs are caused by the charge pump's leakage current and are noted by small spikes one reference frequency away from the output phase. Therefore we measure the reference spurs by measuring the peak power of these small spikes.

Finally to characterize power consumption we connect an ammeter in series with the power supply. We multiply this quantity with the voltage of the powersupply to get the total power consumption of our chip.

Table Of Measured Values

Reference Spurs for SN4

Peak Closeup for SN4

Divider Output for SN4

Final Report.pdf

Our chip with both of our names on the bottom right and left (Shyan and Selasi) - UCLA 2023

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