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16-bit Optimized IIR Digital Bandstop Filter With 75 dB SNR Output Operating At 1MHz Sampling Frequency Using Cascaded Biquads
16-bit Optimized IIR Digital Bandstop Filter With 75 dB SNR Output Operating At 1MHz Sampling Frequency Using Cascaded Biquads
In this project I have designed a finite length bandstop filter with given analog specification and used an architecture of choice and bit width in order to operate with minimal hardware while retaining the needed specification.
Proposed Specifications:
Input sample rate: 1MHz
Passband edges: 75kHz, 175kHz
Stopband edges: 95kHz, 125kHz
Stop band attenuation: 40dB
Passband Ripple: 0.05dB
Passband Group Delay Variation: +/- 5 samples
Minimum output SNR for -6dB full-scale sinusoidal input: 72dB
Magnitude and Phase Response
Passband Group Delay Variation
Design Method and Approach:
Analog Filter Design
In order to convert the analog specifications to digital I had pre-warped the passband and stopband edges, performing under the Nyquist rate, in order to design the analog low-pass filter. The analog design of choice of an Elliptical filter due to it's sharper transition bands as a prevention of quantization effects which will occur later on. The lowest order possible for the analog lowpass filter was found to be 4(8th order for bandstop conversion). The lowpass filter is converted to a bandstop filter and then a bilinear transform was performed on the analog filter to provide it with digital specifications which I would be able to work my design on.
Equalization
The next issue that had come up was the passband group delay variation. In order to get the passband group delay variation between +/- 5 samples, I had implemented two all pass filters(one for each passband), in order to equalize the filter to specification. I had found that having the a 2nd order and 8th order all pass filter equalized the filter to have both linear phase and meet group delay specifications. As shown on the left, group delay varies around 15 samples, under 5 samples for each passband.
Architecture
The next step was design and realization of the architecture of the filter. Multiple design choices were thought. Our primary concern is to meet the SNR requirements whilst keeping less hardware, this includes least number of bits when using finite precision. Scalars tend to use the most hardware during implementation, next is registers and then accumulators. To lower the amount of scalars we have to look at lower order filters, FIR filters require a higher order filter, thus IIR filters becomes the choice despite complexity. Direct Form II tends to have less registers, meaning less hardware intensive components. However this is at the expense of the necessity of more adders which tend to add more round-off noise than registers. In an effort to minimize this a cascaded biquad structure in second order sections is proposed where each biquad is ordered in the cascade from least peaking to most peaking in order to minimize round off effects. The pole zero plot of each filter is used to analyze the distance of the poles of each second order section to the unit circle. The closer to the unit circle, the more peaking occurs. The poles are ordered by distance from the unit circle and then grouped with nearby zeros for each second order section.
Pole-Zero Plot Of Cascaded Second Order Sections
Impulse Response
Bit Width and Quantization Effects
In order to implement the finite word length effects, it is necessary to find the minimum number of bits necessary, whilst in the bounds of the filter's specifications. To mimic finite word length effects, the 'quant' function on MATLAB is used on each scalar, as well each internal node when performing transient analysis of the filter. It is found that 18 bits is the lowest bit width that can be used while meeting specifications.
Transient Analysis and Round Off Effects Testing
A transient analysis is then performed on each internal node to simulate more precise quantization and round off noise effects by quantizing each node of the filter. This test bench is implemented using a nested for loop, where the outer for loop is to inject the input into the first biquad, and the inner for loop takes care each subsequent biquad.
Because we are given a -6dB full scale input, we use an array of a 16 bit -6dB scaled sinusoid placed in the passband with added dither to cover harmonic effects of the quantized input. Each sample of the sinusoid is then run through the for loop which applies the input to each scalar, provided each scalar coefficient in a matrix, and the multiplied coefficient scalar is multiplied to the previous node's output. The final output is captured in a buffer array where all the quantized coefficients are held and an SNR calculation is performed to read the output SNR of the filter. Using this architecture and bit width, the SNR value of the filter is given to be ~75dB, which meets specification. Thus no scaling is needed for each biquad in order to counter round off effects.
Finally I have written code to calculate the amount of hardware required to realize the filter. We know that each biquad requires five scalars, four accumulators, and two registers. Providing us with the required amount of hardware shown in the figure below.
Output Perdiogram
Output SNR and Calculated Hardware
This provides us with an 16-bit IIR filter that can perform at 1MHz sampling frequency using a cascaded biquad of second order sections architecture to fit our specifications.
The filter is designed and implemented using MATLAB.
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